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Features
* * * * * * * * *
Full Compliance with USB Spec Rev 1.1 Four Downstream Ports Full-speed and Low-speed Data Transfers Bus-powered Controller Bus-powered or Self-powered Hub Operation Port Overcurrent Monitoring Port Power Switching 5V Operation with On-chip 3.3V Regulator 24-lead SOIC and 32-lead LQFP
1. Description
The AT43301 is a 5-port USB hub chip supporting one upstream and four downstream ports. The AT43301 connects to an upstream hub or host/root hub via Port0, while the other ports connect to external downstream USB devices. The hub re-transmits the USB differential signal between Port0 and Ports[1:4] in both directions. The AT43301 is designed for very low-cost bus-powered or self-powered hub applications and is available in a 24-lead SOIC and a 32-lead LQFP packages. The 32-lead version of the AT43301, the AT43301-AC, has a 48 MHz clock input. The AT43301 supports the 12 Mb/s full speed as well as 1.5 Mb/s slow speed USB transactions. To reduce EMI, the AT43301's oscillator frequency is 6 MHz even though some internal circuitry operates at 48 MHz.
Low-cost USB Hub Controller AT43301
Figure 1-1.
Pin Configurations
24-lead SOIC Top View
AT43301-SC VCC VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC DP4 DM4 DP3 DM3 DP2 DM2 DP1 DM1 DP0 DM0 VSS
32-lead LQFP Top View
NC DP3 DM3 DP2 DM2 DP1 DM1 NC 32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
CEXT1 OSC1 OSC2 LFT STAT PWR OVC LPSTAT TEST SELF/BUS
NC DM4 DP4 48 VCC VSS CEXT1 NC
1 2 3 4 5 6 7 8
AT43301-AC
NC DP0 DM0 VSS NC SELF/BUS TEST LPSTAT
VSS OSC1 OSC2 LFT STAT PWR NC OVC
9 10 11 12 13 14 15 16
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The AT43301 consists of a Serial Interface Engine, a Hub Repeater, and a Hub Controller. The Serial Interface Engine's tasks are: * Manage the USB communication protocol * USB signaling detection/generation * Clock/data separation, data encoding/decoding, CRC generation/checking * Data serialization/deserialization The Hub Repeater is responsible for: * Providing upstream connectivity between the selected device and the host * Managing connectivity setup and tear-down * Handling bus fault detection and recovery * Detecting connect/disconnect on each port The Hub Controller is responsible for: * Hub enumeration * Providing configuration information to the Host * Providing status of each port to the Host * Controlling each port per host command * Managing port power supply
1.1
Block Diagram
Figure 1-2. AT43301 Block Diagram
UPSTREAM PORT PORT 0
HUB CONTROLLER
SERIAL INTERFACE ENGINE
HUB REPEATER
ENDPOINT 0 ENDPOINT 1
PORT 1
PORT 2
PORT 3
PORT 4
TO DOWNSTREAM DEVICES
Note:
This document assumes that the reader is familiar with the Universal Serial Bus and therefore only describes the unique features of the AT43301 controller. For detailed information about the USB and its operation, the reader should refer to the Universal Serial Bus Specification Version 1.1, September 23, 1998.
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1.2 Pin Assignment
Type: I IS O = Input, = Input, Schmitt Trigger = Output
OD = Output, open drain B V = Bi-directional = Power supply, ground 24-lead SOIC AT43301-SC Pin Assignment
Signal VCC VSS CEXT1 OSC1 OSC2 LFT STAT PWR OVC LPSTAT TEST SELF/BUS VSS DM0 DP0 DM1 DP1 DM2 DP2 DM3 DP3 DM4 DP4 NC Type V V O I O I O O IS IS I IS V B B B B B B B B B B -
Table 1-1.
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
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Table 1-2.
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
32-lead AT43301-AC Pin Assignment
Signal NC DM4 DP4 48 VCC VSS CEXT NC VSS OSC1 OSC2 LFT STAT PWR NC OVC LPSTAT TEST SELF/BUS NC VSS DM0 DP0 NC NC DM1 DP1 DM2 DP2 DM3 DP3 NC Type - B B I V V O - V I O I O O - IS IS I IS - V B B - - B B B B B B -
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Table 1-3.
CEXT1
Signal Descriptions
O External Capacitor. For proper operation of the on-chip regulator, a 0.27 F capacitor must be connected to CEXT1. Upstream Plus USB I/O. This pin should be connected to the CEXT1 pin through an external 1.5 k pull-up resistor. DP0 and DM0 form the differential signal pin pairs connected to the USB host controller or an upstream Hub. Upstream Minus USB I/O. Port Plus USB I/O. This pin should be connected to VSS through an external 15 k resistor. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream USB devices. Port Minus USB I/O. This pin should be connected to VSS through an external 15 k resistor. PLL Filter. For proper operation of the PLL, this pin should be connected through a 2.2 nF capacitor in parallel with a 100 resistor in series with a 10 nF capacitor to ground (VSS). Local Power Status. Schmitt Trigger input pin that is used in the self-powered mode to indicate the condition of the local power supply. This pin should be connected to the local power supply through a 100 k resistor. 48 MHz Select, 32-lead LQFP only. This pin sets the clock input to the AT43301-AC. If it is tied low, a 48 MHz clock must be input to OSC1. If it is tied high (to CEXT1 or to 5V through a 47 k resistor), a 6 MHz crystal must be connected between OSC1 and OSC2, or a 6 MHz clock input to OSC1. Oscillator Input. Input to the inverting 6 MHz oscillator amplifier. Oscillator Output. Output of the inverting oscillator amplifier. Port Overcurrent. This is the Schmitt Trigger input signal used to indicate to the AT43301 that there is a power supply problem with the ports. If OVC is asserted, the AT43301 will de-assert PWR and report the status to the USB Host. Power Switch. This is an output signal to enable or disable the external port power switch for the port power supply. PWR is de-asserted when an overcurrent is detected at OVC. Power Mode. Schmitt Trigger input pin to set power mode of hub. If high, the AT43301 works in the self-powered mode. If low, the bus-powered mode. Status. Output pin which is asserted by the AT43301 whenever it is enumerated. STAT is de-asserted when the hub enters the suspend state. An LED in series with a resistor can be connected to this pin to provide visual feedback to the user. Test. This pin has an internal pull up and should be left unconnected in the normal operating mode. 5V Power Supply from the USB. Ground. No Connect. This pin should be left unconnected.
DP0 DM0 DP[1:4] DM[1:4] LFT LPSTAT
B B B B I I
48 OSC1 OSC2 OVC
I I O I
PWR SELF/BUS
O I
STAT TEST VCC VSS NC
O I V V -
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2. Functional Description
2.1 Summary
The Atmel AT43301 USB hub controller chip contains various features that makes it the ideal solution for very low-cost USB hubs. These features are: on-chip regulator, low-frequency oscillator, bus or self-powered operation, ganged port power switching and global overcurrent protection. Such a hub can be a stand-alone hub used with portable computers to allow convenient connectivity to standard desktop peripheral devices. Alternatively, the hub can be added to an existing non-USB peripheral such a keyboard. The AT43301 provides 4 downstream USB ports and can operate in a self-powered or bus-powered mode.
2.2
USB Ports
The AT43301's upstream port, Port0, is a full speed port. A 1.5 k pull-up resistor to the 3.3V regulator output, CEXT, is required for proper operation. The downstream ports support both full-speed as well as low-speed devices. 15 k pull down resistors are required at their inputs. Full speed signal requirements demand controlled rise/fall times and impedance matching of the USB ports. To meet these requirements, 22 resistors must be inserted in series between the USB data pins and the USB connectors.
2.3
Hub Repeater
The Hub Repeater is responsible for port connectivity setup and teardown. It also supports exception handling such as bus fault detection and recovery, and connect/disconnect detection. Port0 is the root port and is connected to the root hub or an upstream hub. When a packet is received at Port0, the AT43301 propagates it to all the enabled downstream ports. Conversely, a packet from a downstream port is transmitted from Port0. The AT43301 supports downstream port data signaling at both 1.5 Mb/s and 12 Mb/s. Devices attached to the downstream ports are determined to be either full speed or low speed depending which data line (DP or DM) is pulled high. If a port is enumerated as low speed, its output buffers operate at a slew rate of 75-300 ns, and the AT43301 will not propagate any traffic to that port unless it is prefaced with a preamble PID. Low speed data following the preamble PID is propagated to both low- and full-speed devices. The AT43301 will enable low-speed drivers within four full-speed bit times of the last bit of a preamble PID, and will disable them at the end of an EOP. The upstream traffic from all ports is propagated by Port0 using the full speed 4-20ns slew rate drivers. All the AT43301 ports independently drive and monitor their DP and DM pins so that they are able to detect and generate the `J', `K', and SE0 bus signaling states. Each hub port has singleended and differential receivers on its DP and DM lines. The ports' I/O buffers comply with the voltage levels and drive requirements as specified in the USB Specifications Rev 1.0. The Hub Repeater implements a frame timer which is timed by the 12 MHz USB clock and gets reset every time an SOF token is received from the host.
2.4
Serial Interface Engine
The Serial Interface Engine handles the USB communication protocol. It performs the USB clock/data separation, the NRZI data encoding/decoding, bit stuffing, CRC generation and checking, USB packet ID decoding and generation, and data serialization and de-serialization.
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The on-chip phase locked loop generates the high frequency clock for the clock/data separation circuit.
2.5
Power Management
A hub is allowed to draw up to 500 mA of power from the host or upstream hub. The AT43301's itself and its external circuitry typically consume about 24 mA. Therefore, in the bus-powered mode, 100 mA is available for each of the hub's downstream devices. In the self-powered mode, an external power supply is required which must be capable of supplying 500 mA per port. The power supplied to the ports is monitored and controlled by the AT43301. The AT43301 reports overcurrent on a global basis. The overcurrent signal, which needs to be detected by an external device, is read through the OVC pin. A logic low at OVC is interpreted as an overcurrent condition. This could be caused by an overload, or a short circuit, and causes the AT43301 to set the Over-Current Indicator bit of the Hub Status Field, wHubStatus, as well as the Over-Current Indicator Change bit of the Hub Change Field, wHubChange. At the same time, power to the ports is switched off by de-asserting PWR. An external device is needed to perform the actual switching of the ports' power under control of the AT43301. Any type of suitable switch or device is acceptable. However, the switch should have a low-voltage drop across it even when the port absorbs full power. In its simplest form, this switch can be a high side MOSFET switch. The advantage of using a MOSFET switch is its very low-voltage drop. The power control pin, PWR, is asserted only when a SetPortFeature[PORT-POWER] request is received from the host. PWR is de-asserted under the following conditions: 1. Power up 2. Reset and initialization 3. Overcurrent condition 4. Requested by the host though a ClearPortFeature[PORT_POWER] for ALL the ports
2.5.1
Self-powered Mode In the self-powered mode, power to the downstream ports must be supplied by an external power supply. This power supply must be capable of supplying 500 mA per port or 2A total with good voltage tolerance and regulation. At full hub operating power, that is all downstream ports drawing 500 mA each, the minimum voltage at the downstream port connector must be 4.75V. The USB specification requires that the voltage drop at the power switch and board traces be no more than 100 mV. A good conservative maximum drop at the power switch itself should be no more than 75 mV. Careful design and selection of the power switch and PC board layout is required to meet the specifications. When using a MOSFET switch, its resistance must be 40 m or less under worst case conditions. A suitable MOSFET switch for an AT43301 based hub is an integrated highside MOSFET switch such as the Micrel MIC2505.
2.5.2
Bus-Powered Mode In the bus-powered mode all the power for the hub itself as well as the downstream ports is supplied by the root hub or upstream hub through the USB. Only 100 mA is available for each of the hub's downstream devices and therefore only low-power devices are supported. The power switch works exactly like the self-powered mode, except that the allowable switch resistance is higher: 140 m or less under the worst case condition. An example of a suitable high side switch for a bus-powered hub is the Micrel MIC2525.
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The diagrams of Figure 2-1 and Figure 2-2 show examples of the power supply and power management scheme in the self-powered mode and bus-powered mode using an integrated switch with built-in overcurrent protection. Figure 2-1. Bus-powered Hub
BUS_POWER GND U1 GND AT43301 PWR OVC PORT_POWER GND PORT_POWER GND FLG OUT SWITCH PORT_POWER GND PORT_POWER GND VCC
U2 CTL IN
TO DOWNSTREAM DEVICES
Figure 2-2.
Self-powered Hub
BUS_POWER GND U1 GND AT43301 PWR OVC PORT_POWER GND PORT_POWER GND FLG OUT SWITCH PORT_POWER GND PORT_POWER GND VCC
PS5 POWER SUPPLY 5V OUT GND
U2 CTL IN
TO DOWNSTREAM DEVICES
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2.6 Hub Controller
The Hub Controller of the AT43301 provides the mechanism for the host to enumerate the hub and the AT43301 to provide the host with its configuration information. It also provides a mechanism for the host to monitor and control the downstream ports. The Hub Controller supports two endpoints, Endpoint0 and Endpoint1. The Hub Controller maintains a status register, Controller Status Register, which reflects the AT43301's current settings. At power up, all bits in this register will be set to 0's. Table 2-1.
Bit 0
Controller Status Register
Value 0 1 Description Set to 0 or 1 by a Set_Configuration Request Hub is not currently configured Hub is currently configured Set to 0 or 1 by ClearFeature or SetFeature request. Default value is 0. Hub is currently not enabled to request remote wakeup Hub is currently enabled to request remote wakeup Endpoint0 is not stalled Endpoint0 is stalled Endpoint1 is not stalled Endpoint1 is stalled
Function Hub configuration status
1
Hub remote wakeup status
0 1 0 1 0 1
2 3
Endpoint0 STALL status Endpoint1 STALL status
2.6.1
Endpoint 0 Endpoint 0 is the AT43301's default endpoint used for enumeration of the hub and exchange of configuration information and requests between the host and the AT43301. Endpoint 0 supports control transfers. The Hub Controller supports the following descriptors through Endpoint 0: Device Descriptor, Configuration Descriptor, Interface Descriptor, Endpoint Descriptor, and Hub Descriptor. These descriptors are described in detail elsewhere in this document. Standard USB Device Requests and class-specific Hub Requests are also supported through Endpoint 0. There is no endpoint descriptor for Endpoint0.
2.6.2
Endpoint 1 Endpoint1 is used by the Hub Controller to send status change information to the host. This endpoint supports interrupt transfers. The Hub Controller samples the changes at the end of every frame at time marker EOF2 in preparation for a potential data transfer in the subsequent frame. The sampled information is stored in a byte wide register, the Status Change Register, using a bitmap scheme.
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Each bit in the Status Change Register corresponds to one port as shown below: Table 2-2.
Bit 0 1 2 3 4 5-7
Status Change Register
Function Hub status change Port1 status change Port2 status change Port3 status change Port4 status change Reserved Value 0 1 0 1 0 1 0 1 0 1 000 Meaning No change in status Change in status detected No change in status Change in status detected No change in status Change in status detected No change in status Change in status detected No change in status Change in status detected Default values
An IN Token packet from the host to Endpoint 1 indicates a request for port change status. If the hub has not detected any change on its ports, or any changes in itself, then all bits in this register will be 0 and the Hub Controller will return a NAK to requests on Endpoint1. If any of bits 0-4 is 1, the Hub Controller will transfer the whole byte. The Hub Controller will continue to report a status change when polled until that particular change has been removed by a ClearPortFeature request from the Host. No status change will be reported by Endpoint 1 until the AT43301 has been enumerated and configured by the host.
2.7
Oscillator and Phase-Locked-Loop
All the clock signals required to run the AT43301 are derived from an on-chip oscillator. To reduce EMI and power dissipation in the system, the AT43301 is designed to operate with a 6 MHz crystal. An on-chip PLL generates the high frequency for the clock/data separator of the Serial Interface Engine. In the suspended state, the oscillator circuitry is turned off. To assure quick startup, a crystal with a high Q, or low ESR, should be used. To meet the USB hub frequency accuracy and stability requirements for hubs, the crystal should have an accuracy and stability of better than 100 ppm. Even though the oscillator circuit would work with a ceramic resonator, its use is not recommended because a resonator would not have the frequency accuracy and stability. A 6 MHz parallel resonance quartz crystal with a load capacitance of approximately 10 pF is recommended. The oscillator is a special low-power design and in most cases no external capacitors and resistors are necessary. If the crystal requires a higher value capacitance, external capacitors can be added to the two terminals of the crystal and ground to meet the required value. If the crystal used cannot tolerate the drive levels of the oscillator, a series resistor between OSC2 and the crystal pin is recommended. The clock can also be externally sourced. In this case, connect the clock source to the OSC1 pin, while leaving OSC2 pin floating. The switching level at the OSC1 pin can be as low as 0.47V (see "Electrical Specification" on page 12) and a CMOS device is required to drive this pin to maintain good noise margins at the low switching level. The 32-lead AT43301-AC can also be driven by a 48 MHz external clock instead. In this case, connect the 48N pin to ground.
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For proper operation of the PLL, an external RC filter consisting of a series RC network of 100 and 10 nF in parallel with a 2 nF capacitor must be connected from the LFT pin to VSS.
2.8
Status Pin
The status pin, STAT, is provided to allow feedback to the user. If an LED and a series resistor is connected between STAT and VCC, the LED will light when the hub is enumerated. During an overcurrent condition, the LED will blink. It will continue to blink until the host turns off the power to the ports or until the hub is re-enumerated. The I/O pins of the AT43301 should not be directly connected to voltages less than VSS or more than the voltage at the CEXT pins. If it is necessary to violate this rule, insert a series resistor between the I/O pin and the source of the external signal source that limits the current into the I/O pin to less than 0.2 mA. Under no circumstance should the external voltage exceed 5.5V. To do so will put the chip under excessive stress. Figure 2-3. External Oscillator and PLL Circuit
U1 OSC1 OSC2 LFT C2 2nF
Y1 6.000 MHz R1 100 C1 10nF
AT43301
2.9
Power Supply
The AT43301 is powered from the USB bus, but has an internal voltage regulator to supply the 3.3V operating power to its circuitry. For proper operation, an external high quality, low ESR, 0.27 F, or larger, capacitor should be connected to the output of the regulator, CEXT1 and ground. The CEXT1 pin can also be used to supply the voltage to the 1.5 k pull up resistor at Port 0's DP pin. To provide the best operating condition for the AT43301, careful consideration of the power supply connections are recommended. Use short, low impedance connections to all power supply lines: VCC and VSS. Use sufficient decoupling capacitance to reduce noise: 0.1 F of high quality ceramic capacitor soldered as close as possible to the VCC and VSS package pins are recommended. The AT43301 can also operate directly off a 3.3V power supply. In this case, leave the VCC pin floating and connect the 3.3V power to CEXT1.
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3. Electrical Specification
3.1
VCC5 VI VO TO TS *NOTICE:
Absolute Maximum Ratings*
Parameter 5V Power Supply DC Input Voltage DC Output Voltage Operating Temperature -0.3V -0.3 -40 Condition Min Max 5.5 VCEXT + 0.3 4.6 max VCEXT + 0.3 4.6 max +125 Unit V V V C
Symbol
Storage Temperature -65 +150 C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3.2
DC Characteristics
Power Supply
Parameter 5V Power Supply 5V Supply Current Suspended Device Current Condition Min 4.4 Max 5.25 24 150 Unit V mA A
The values shown in this table are valid for TA = 0C to 85C, VCC = 4.4V to 5.25V, unless otherwise noted. Table 3-1.
Symbol VCC ICC ICCS
Table 3-2.
Symbol VIH VIHZ VIL VDI VCM VOL1 VOH1 VCRS CIN
USB Signals: DPx, DMx
Parameter Input Level High (driven) Input Level High (floating) Input Level Low Differential Input Sensitivity Differential Common Mode Range Static Output Low Static Output High Output Signal Crossover Input Capacitance RL of 1.5 k to 3.6V RL of 15 k to GND 2.8 1.3 DPx and DMx 0.2 0.8 2.5 0.3 3.6 2.0 20 Condition Min 2.0 2.7 3.6 0.8 Max Unit V V V V V V V V pF
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Table 3-3.
Symbol VOL2 COUT VIL3 VIH3 COUT VOH2
PWR, STAT, OVC
Parameter Output Low Level, PWR, STAT Output Capacitance Input Low Level Input High Level Output Capacitance Output High Level, PWR 1 MHz IOH = 4 mA VCEXT - 0.5 0.7VCEXT 10 Condition IOL = 4 mA 1 MHz Min Max 0.5 10 0.3VCEXT Unit V pF V V pF V
Table 3-4.
Symbol VLH VHL CX1 CX2 C12 tsu DL Note:
Oscillator Signals: OSC1, OSC2
Parameter OSC1 Switching Level OSC1 Switching Level Input Capacitance, OSC1 Output Capacitance, OSC2 OSC1/2 Capacitance Start-up Time Drive Level 6 MHz, fundamental VCC = 3.3V, 6 MHz crystal, 100 equiv series resistor Condition Min 0.47 0.67 Max 1.20 1.44 17 17 1 2 150 Unit V V pF pF pF ms W
OSC2 must not be used to drive other circuitry.
3.3
AC Characteristics
DPx, DMx Driver Characteristics, Full Speed Operation
Parameter Rise Time Fall Time tR/tF Matching Driver Output Resistance
(1)
Table 3-5.
Symbol tR tF tRFM ZDRV Note:
Condition CL = 50 pF CL = 50 pF
Min 4 4 90
Max 20 20 110 44
Unit ns ns %
Steady state drive
28
1. With external 22 series resistor.
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Table 3-6.
Symbol tDRATE tFRAME tRFI tRFIADJ tDJ1 tDJ2 tFDEOP tJR1 tJR2 tFEOPT tFEOPR tFST Note:
DPx, DMx Source Timings, Full Speed Operation
Parameter Full Speed Data Rate(1) Frame Interval
(1) (1)
Condition Average bit rate
Min 11.97 0.9995
Max 12.03 1.0005 42.0 126.0
Unit Mb/s ms ns ns ns ns ns ns ns ns ns
Consecutive Frame Interval Jitter
No clock adjustment With clock adjustment -3.5 -4.0 -2.0 -18.5 -9.0 160.0 82.0
Consecutive Frame Interval Jitter(1) Source Diff Driver Jitter To Next Transition For Paired Transitions Source Jitter for Differential Transition to SEO Transitions Recvr Data Jitter Tolerance To Next Transition For Paired Transitions Source SEO interval of EOP Receiver SEO interval of EOP Width of SEO interval during differential transition 1. With 6.000 MHz, 100 ppm crystal.
3.5 4.0 5.0 18.5 9.0 175.0
14.0
ns
Table 3-7.
Symbol tR tF tRFM
DPx, DMx Driver Characteristics, Low-speed Operation
Parameter Rise time Fall time tR/tF matching Condition CL = 200 - 600 pF CL = 200 - 600 pF Min 75.0 75.0 80.0 Max 300.0 300.0 125.0 Unit ns ns %
Table 3-8.
Symbol tHDD2 tHDJ1 tHDJ2 tFSOP tFEOPD tFHESK
DPx, DMx Hub Timings, High-Speed Operation
Parameter Hub Differential Data Delay without Cable Hub Diff Driver Jitter To Next Transition For Paired Transitions Data Bit Width Distortion after SOP Hub EOP Delay Relative to tHDD Hub EOP Output Width Skew -3.0 -1.0 -5.0 0 -15.0 Condition Min Max 44.0 3.0 1.0 5.0 15.0 15.0 Unit ns ns ns ns ns ns
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Table 3-9.
Symbol tLHDD tLHDJ1 tLHDJ2 tLUHJ1 tLUHJ2 tSOP tLEOPD tLHESK
DPx, DMx Hub Timings, Low-speed Operation
Parameter Hub Differential Data Delay Downstr Hub Diff Driver Jitter To Next Transition, downst For Paired Transitions, downst To Next Transition, upstr For Paired Transitions, upstr Data Bit Width Distortion after SOP Hub EOP Delay Relative to tHDD Hub EOP Output Width Skew -45.0 -15.0 -45.0 -45.0 -60.0 0 -300.0 Condition Min Max 300.0 45.0 15.0 45.0 45.0 60.0 200.0 300.0 Unit ns ns ns ns ns ns ns ns
Table 3-10.
Symbol tDCNN
Hub Event Timings
Condition Min 2.5 2.5 2.5 2.5 Max 2000.0 12000.0 2.5 10000.0 100.0 Only for a SetPortFeature (PORT_RESET) request 10.0 2.5 2.5 20.0 100.0 10000.0 23 Unit s s s s s ms s s FS bit time
Parameter Time to Detect a Downstream Port Connect Event Awake Hub Suspended Hub Time to Detect a Disconnect Event on Downstream Port Awake Hub Suspended Hub Time from Detecting Downstream Resume to Rebroadcast Duration of Driving Reset to a Downstream Device Time to Detect a Long K from Upstream Time to Detect a Long SEO from Upstream Duration of repeating SEO Upstream
tDDIS
tURSM tDRST tURLK tURLSEO tURPSEO
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4. Timing Waveforms
Figure 4-1. Data Signal Rise and Fall Time
RISE TIME VCRS
10% 90% 90%
FALL TIME
10%
DIFFERENTIAL DATA LINES tR tF
Figure 4-2.
Full-speed Load
TxD+ RS CL RS CL
TxD-
CL = 50pF
Figure 4-3.
Low-speed Downstream Port Load
TxD+ RS CL RS CL 3.6V 1.5K
TxD-
CL = 200pF to 600pF
Figure 4-4.
Differential Data Jitter
TPERIOD DIFFERENTIAL DATA LINES CROSSOVER POINTS CONSECUTIVE TRANSITIONS N*TPERIOD+TXJR1 PAIRED TRANSITIONS N*TPERIOD+TXJR2
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Figure 4-5. Differential-to-EOP Transition Skew and EOP Width
TPERIOD DIFFERENTIAL DATA LINES DIFF. DATA-toSE0 SKEW N*TPERIOD+TDEOP SOURCE EOP WIDTH: TFEOPT TLEOPT RECEIVER EOP WIDTH: TFEOPR, TLEOPR CROSSOVER POINT EXTENDED
Figure 4-6.
Receiver Jitter Tolerance
TPERIOD DIFFERENTIAL DATA LINES TJR CONSECUTIVE TRANSITIONS N*TPERIOD+TJR1 CONSECUTIVE TRANSITIONS N*TPERIOD+TJR1 TJR1 TJR2
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Figure 4-7.
Hub Differential Delay, Differential Jitter, and SOP Distortion
DOWNSTREAM PORT VSS HUB DELAY DOWNSTREAM THDD1 CROSSOVER POINT UPSTREAM PORT VSS HUB DELAY UPSTREAM THDD2 CROSSOVER POINT CROSSOVER POINT
UPSTREAM END OF CABLE VSS DIFFERENTIAL DATA LINES VSS
50% POINT OF INITIAL SWING
A. DOWNSTREAM HUB DELAY WITH CABLE
B. UPSTREAM HUB DELAY WITHOUT CABLE
DOWNSTREAM PORT VSS UPSTREAM PORT OR END OF CABLE VSS
CROSSOVER POINT
HUB DELAY UPSTREAM THDD1, THDD2
CROSSOVER POINT
C. UPSTREAM HUB DELAY WITH OR WITHOUT CABLE
Hub Differential Jitter: THDJ1 = THDDX(J) - THDDX(K) or THDDX(K) - THDDX(J) Consecutive Transitions THDJ2 = THDDX(J) - THDDX(J) or THDDX(K) - THDDX(K) Paired Transitions Bit After Sop Width Distortion (Same as Data Jitter for Sop and Next J Transition): TSOP = THDDX(NEXTJ) - THDDX(SOP) Low-speed timings are determined in the same way for: TLHDD, TLDHJ1, TLDJH2, TLUHJ1, TLUJH2, and TLSOP
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Figure 4-8. Hub EOP Delay and EOP Skew
50% POINT OF INITIAL SWING UPSTREAM END OF CABLE VSS DOWNSTREAM PORT VSS A. DOWNSTREAM EOP DELAY WITH CABLE TEOPTEOP+ CROSSOVER POINT EXTENDED UPSTREAM PORT VSS DOWNSTREAM PORT VSS B. DOWNSTREAM EOP DELAY WITHOUT CABLE TEOPTEOP+ CROSSOVER POINT EXTENDED CROSSOVER POINT EXTENDED
DOWNSTREAM PORT VSS UPSTREAM PORT OR END OF CABLE VSS
CROSSOVER POINT EXTENDED
TEOP-
TEOP+
CROSSOVER POINT EXTENDED
C. UPSTREAM EOP DELAY WITH OR WITHOUT CABLE
EOP Delay: TEOPD = TEOP - THDDX EOP Skew: THESK = TEOP + -TEOPLow-speed timings are determined in the same way for: TLEOPD and TLHESK
19
1137J-USB-01/06
Figure 5-1.
5. Schematic Diagrams
7
12
8
U1
STAT PWR
VCC R7 22 CEXT R9 22 R8 DM1 DP1 DM2 DP2 R11 22 18 19 16 17 22
C12 4.7UF
SELF/BUS
+
3
OVC
1
9
5
6
OSC1
OSC2
4
5
R4 100 C3 2.2nF Y1 C2 0.01UF 6.000MHz
2 13
VSS VSS
8 7 6 5 4 3 2 1
9 10 11 12 13 14 15 16
20
VBUS
AT43301
Bus-powered Hub
VBUS
PWR
R16 47K R5 470 1N4148 LED D2 D1 OVC
DM1 DP1
L1 C1 0.27UF R3 1.5K 10 LPSTAT
FB
DM2 DP2 R10 22 DM3 DP3 R13 22 R12 22 DM4 DP4 R14 22
JP1 14 15 R2 11 24 TEST NC LFT DM4 DP4 6 22 23 DM0 DP0 DM3 DP3 22 L11 FB
22 R1
AT43301
20 21
USB-B
1 2 3 4
RP1 15K
The following pages show schematic diagrams of an AT43301 based bus-powered hub and selfpowered hub.
1137J-USB-01/06
Figure 5-2.
VBUS IN NC EN NC L3 FB 3 + C4 0.1uF C5 0.1uF + FLG GND MIC2525-2 C8 47uF DM2 C9 DP2 47uF 4 DM1 DP1 OUT OUT 1 2
7 5
8 6
9 10
L13 FB
5 6 7 8
L4 DM3 DP3
FB 1 2 3 4 L5 FB L14 FB
9 10
11 12
C10 47uF
DM4 C11 DP4 47uF + +
C6 0.1uF C7 0.1uF
L15 FB
5 6 7 8
11 12
1137J-USB-01/06
Bus-powered Hub
VBUS
U2 L2 FB
PWR
L12 FB
1 2 3 4
JP2 USB-2A
OVC
JP3 USB-2A
AT43301
21
Figure 5-3.
7
12
8
U1 STAT PWR VCC R7 22 CEXT R9 22 R8 DM1 DP1 18 19 R11 22 16 17 22 OVC 1 3 R6 47K 10 LPSTAT DM2 DP2 SELF/BUS 9
5
6
OSC1
OSC2
4
5
R4 100 C3 2.2nF Y1 C2 0.01UF 6.000MHz
2 13
VSS VSS
8 7 6 5 4 3 2 1
9 10 11 12 13 14 15 16
22
VLOCAL
AT43301
R5 Q1 2N4401 470 R16 D1 LED R35 470 47K
Self-powered Hub
VBUS
PWR
OVR
C1 R3 1.5K 22 R1 14 15 R2 11 24 TEST NC LFT DM4 DP4 6 22 23 DM0 DP0 DM3 DP3 22
DM1 DP1 DM2 DP2 R10 22 DM3 DP3 R13 22 R12 22 DM4 DP4 R14 22
L1
0.27UF
FB
AT43301
20 21
JP1
USB-B
1 2 3 4
L11 FB
RP1 15K
1137J-USB-01/06
Figure 5-4.
7 5 IN IN CTL GATE L3 GND C8 100 UF + + DM2 C9 DP2 100 UF 3 FLG MIC2505-2 4 DM1 DP1 FB OUT OUT 1 2
6 8
9 10
C4 0.1uF C5 0.1uF
L13 FB
5 6 7 8
L4 DM3 DP3
FB 1 2 3 4 L5 FB L14 FB
9 10
11 12
C10 100 UF
DM4 C11 DP4 100 UF + +
C6 0.1uF C7 0.1uF
L15 FB
5 6 7 8
11 12
1137J-USB-01/06
VLOCAL 0.1 UF C14
J1
4.7 UF
C15
Self-powered Hub
1 2
+
CON2
U2 L2 FB
PWR
L12 FB
1 2 3 4
JP2 USB-2A
OVC
JP3 USB-2A
AT43301
23
6. Ordering Information
6.1 AT43301 Standard Package Options
Package 24S - SOIC 32AA - LQFP Operation Range Commercial (0C to 70C) Commercial (0C to 70C)
Ordering Code AT43301-SC AT43301-AC
6.2
AT43301 Green Package Options (Pb/Halide-free/RoHS Compliant)
Package 32AA - LQFP 24S - SOIC Operation Range Industrial (-40C to 85C) Industrial (-40C to 85C)
Ordering Code AT43301-AU AT43301-SU
Package Type 24S 32AA 24-lead (0.300 in. body) Plastic Gull Wing Small Outline Package (SOIC) 32-lead, Low-profile (1.4 mm) Plastic Quad Flat Package (LQFP)
24
AT43301
1137J-USB-01/06
AT43301
7. Packaging Information
7.1 32AA - LQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 1.35 8.75 6.90 8.75 6.90 0.30 0.09 0.45 NOM - - 1.40 9.00 7.00 9.00 7.00 - - - 0.80 TYP MAX 1.60 0.15 1.45 9.25 7.10 9.25 7.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation BBA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 32AA, 32-lead, 7 x 7 mm Body Size, 1.4 mm Body Thickness, 0.8 mm Lead Pitch, Low Profile Plastic Quad Flat Package (LQFP) DRAWING NO. 32AA REV. B
R
25
1137J-USB-01/06
7.2
24S - SOIC
B
D1
PIN 1 ID PIN 1
D
e
E A
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN - 0.10 10.00 7.40 15.20 0.33 0.40 0.23 NOM - - - - - - - - 1.27 BSC MAX 2.65 0.30 10.65 7.60 15.60 0.51 1.27 0.32 NOTE
A1
A A1 D D1
0 ~ 8
L1
E B L
L
L1 e
06/17/2002 2325 Orchard Parkway San Jose, CA 95131 TITLE 24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) DRAWING NO. 24S REV. B
R
26
AT43301
1137J-USB-01/06
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1137J-USB-01/06

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